1. Field of the Invention
The present invention relates to the field of semiconductor packaging, in particular, surface mountable packaging. More specifically, the present invention relates to packaging a high power very large scale integration (VLSI) semiconductor die in a thermally efficient and surface mountable manner.
2. Background
Surface mountable semiconductor packages including the relatively new ball grid array (BGA) packages are well known in the art of semiconductor packaging. The relatively new BGA packages take advantage of the more traditional pin grid array (PGA) design and surface mountable technology. Typically, a basic surface mountable semiconductor package comprises a VLSI die, a substrate, a heat slug, a lid, and a heat sink. The substrate has a stepped cavity at its center, and electrical contacts at its underside. The electrical contacts may be in either PGA or BGA format. The heat slug is first attached to the top side of the substrate using an adhesive material. The inactive side of the VLSI die is then attached to the underside of the heat slug using a first film of thermal adhesive, and the leads of the VLSI die are wire bonded to the substrate. Then the lid is attached to the cavity opening at the underside of the substrate protecting the active side of the VLSI die. The semiconductor package is then surface mounted to a printed wiring board (PWB) by joining the electrical contacts at the underside with complementary electrical contacts at a land pattern on the PWB. Lastly, the heat sink is attached to the top side of the heat slug with a second layer of thermal adhesive material.
Although thermal adhesive materials are used to attach the inactive side of the VLSI die and the heat sink to opposite sides the heat slugs, experience has shown that each layer of thermal adhesive material nevertheless increases the temperature in the enclosed cavity of the substrate by about 0.5 C./watt. Thus, for a VLSI die with 60 or 70 watts applied power, one layer of adhesive material increases the temperature in the enclosed cavity of the substrate by about 30 to 35 C. It is well known that heat generated by the VLSI die during operation is detrimental to the performance and reliability of the VLSI die as well as the neighboring electronic components. Various heat removal techniques including embedded heat pipes with air or fluid coolants are known in the art, and can be employed to lower the temperature in the enclosed cavity of the substrate. However, these techniques tend to increase the complexity and cost of the semiconductor package.
An alternate approach is to attach the heat sink to the top side of the substrate, and then attach the inactive side of the VLSI die to the heat sink directly. However, since wire bonding packaging equipment available today typically cannot handle a substrate with a large heat sink attached to it, either a different approach for bonding the leads of the VLSI die to the wiring planes of the substrate is provided or customized wire bonding equipment will have to be provided. Neither approaches are desirable. Additionally, even if the wire bonding equipment can be easily and cheaply modified to accommodate the attached heat sink, it still presents a problem to the surface mounting equipment. In particular, if the electrical contacts of the substrate are BGA bumps, the preattached heat sink will block the BGA bumps and prevent the surface mount equipment from focusing the laser beam on the bumps to solder them onto the land pattern of the PWB.
Thus, it is desirable to be able to package a high applied power VLSI die in a manner that is thermally efficient, surface mountable, and low cost. As will be disclosed, the present invention provides for such a semiconductor package which advantageously achieves the desired results.